The fetch-decode-execute cycle and interrupts

The cycle, in register transfer terms

Learn it as a sequence of register transfers, because that is how it is marked:

$\text{MAR} \leftarrow [\text{PC}]$ — copy the next address into MAR
$\text{PC} \leftarrow [\text{PC}] + 1$ — increment ready for the following instruction
$\text{MDR} \leftarrow [[\text{MAR}]]$ — fetch the contents of that memory location
$\text{CIR} \leftarrow [\text{MDR}]$ — move the instruction into the CIR
then decode the opcode in the control unit, and execute.

Why PC is incremented so early

Incrementing before execution means a jump instruction can simply overwrite the PC during execute, and the cycle continues correctly from the new address. Explaining this is a standard three-mark answer.

Interrupts

An interrupt is a signal from hardware or software requesting the processor's attention — a key press, a completed disk transfer, a division by zero. At the end of the current cycle the processor checks the interrupt register. If an interrupt is present and has higher priority than the current task, the processor pushes the contents of the registers (the process state) onto the stack, loads the address of the appropriate interrupt service routine, runs it, then pops the saved state back and resumes.

Two details that earn marks

First, the check happens at the end of a cycle, not mid-instruction — otherwise the machine state would be inconsistent. Second, saving to a stack is what allows nested interrupts: a higher-priority interrupt can interrupt an interrupt, and the last-in-first-out order restores everything correctly.